A multilayer printed wiring board is a printed wiring board comprising a plurality of conductive wiring layers with interim dielectric layers. By installing lands for connection on the wiring layers, forming a through-hole penetrating all of the board's wiring and dielectric layers and coating this through-hole with conductive material, e.g., copper, a method for electrically connecting separate conductive wiring layers using the through-hole is possible. A through-hole is thus understood to pass through the board's entire thickness.
In addition, a conductive via hole can also be used as a means for electrically connecting selected adjacent layers. A via hole is typically a small hole provided in a dielectric layer, having an interior surface plated with conductive material, and which serves to electrically connect upper and lower conductive layers on opposite sides of the dielectric. A via hole is thus understood to comprise an internally positioned conductive hole within the final board structure, as opposed to a through-hole which passes entirely through the board. For forming a via hole, a buildup method is typically employed. As shown in FIGS. 1 to 4, such a method typically involves the building up of a plurality of individual layers by repeating the process of forming a singular insulating resin layer. Via holes may then be provided along with various conductive layers to form a subcomposite which is then laminated together with other laminates in a defined pattern of alignment. To take an example, as shown in FIG. 1, a photosensitive insulating (dielectric) resin film 110 is applied on a substrate 100 having connecting land 105. This application may be performed by spin coating, screen printing, curtain coating or the like methods. As shown in FIG. 2, a via hole 130 is formed in dielectric 110 above on the land 105 by performing a known photolithographic method typically involving exposure, development, and etching steps to provide, typically, a predetermined pattern of such holes in the photosensitive insulating resin layer. The etching step may be performed using known dry and/or wet methodology. Then, as shown in FIG. 3, a conductive layer 140 is formed (e.g.,plated) with conductive material on the via hole 130. Furthermore, as shown in FIG. 4, a second insulating resin layer 150 can now be added to obtain a double insulative layered subassembly. Since only holes formed internally at required places are deemed sufficient, this buildup method is excellent in that the degree of freedom for wiring is so much the greater compared to the through-hole version involving total board penetration.
In the aforedefined buildup method, where it is desired to electrically connect spaced apart points A and B, (e.g., on dielectric layers 110 and 180 as shown in FIG. 5), a second via hole 160 is typically formed on the third (interim) insulating layer 150. Hole 160 is situated slightly offset from a position directly above the first via hole 130 formed in first insulating layer 110. The illustrated via hole 190 is similarly formed on the respective insulating layer 180 a slight distance apart from the interconnecting via hole 160 in insulating layer 150. Accordingly, a via hole has been formed not directly above another via hole to electrically connect two non-adjacent layers (e.g., 180 and 110).
In a structure such as shown in FIG. 5, however, a total area proportional to nearly a square of d.sub.1 is required for electrically connecting points A and B through such a via hole as 160. d.sub.1 is understood to be the dimension of the maximum distance between the respective outermost internal sidewalls of holes 130 and 160. Understandably, d.sub.1 becomes relatively large because of the oblique positioning orientation between holes 130 and 160. Such a connection (by forming the next via hole obliquely above a first via hole), does not satisfy today's demands for higher circuit densities.
It has been considered for ensuring such demand to form two via holes directly above one another, for example, as shown in FIG. 6. In FIG. 6, a first via hole 130 is formed on a first insulating layer 110 and a second via hole 160 is formed right above this first via hole within the second insulating layer 150. Then, a plated layer 170 is formed on the second via hole 160 to thereby provide connection between a point A on the second insulating layer 150 (where, most likely, additional circuitry will also be located) and a point B on the lower substrate 100. There are various problems associated with the FIG. 6 approach, as described in greater detail hereinbelow.
Firstly, the second insulating layer 150 is typically etched by a wet process (or the like) in forming the via hole 160. This etching process takes considerable time due primarily to the need for etching about twice the normal depth. When performing such a relatively long duration etching, etching occurs not only in the depth (vertical) direction but also in a substantially radial direction. Thus the diameter (d.sub.2) of the resulting hole has a tendency to become relatively large, another unacceptable feature. As with the example in FIG. 5, a total area for connecting point A and B can be estimated to be approximately the square of d.sub.2.
A second problem associated with the FIG. 6 approach is that the etching procedure might not always be completely performed. If incomplete, the second insulating layer 150 may not be entirely etched out such that some of its material (172) remains on the bottom of the lower via hole 130. An excessive amount of such material 172, being dielectric, may adversely affect a desired connection between the plated layer 140 formed on the first via hole 130 and a plated layer 170 formed on the second via hole.
Thus, simply forming another via hole directly over a lower via hole may not meet the stringent requirements of reduced overall board area consumption and increased operational reliability.
As a structure for electrically connecting two non-adjacent layers, consideration has also been given to using no via hole(s). For example, use of a post (called stud) composed of conductive materials has been considered. The process of doing so is illustrated in FIGS. 7-11. Firstly, after applying a photoresist (210) or the like on a substrate 200 and forming an opening (or openings) in the resist, metal or other conductive materials 220 is deposited in the opening (e.g., using a technique such as plating). Thereafter, as shown in FIG. 8, the resist is removed using known techniques to thereby leave only the stud (220) atop the substrate. Then, as shown in FIG. 9, an insulating resin layer 230 is provided in such a manner as to completely cover stud (220) and the remaining exposed surface of the substrate. The resin's upper surface and part of the stud (220) are then smoothed to provide the configuration depicted in FIG. 10. Repeating this process, a structure for electrically connecting two points A and B (FIG. 11) can be obtained. This method, not utilizing etching, only has a small consumed area (proportional to a square of d.sub.3) in the structure required for electrically connecting points A and B. Greater densities are thus possible compared to the foregoing other procedures. However, this method also has disadvantages. Firstly, because the insulating layer 230 is applied without supporting the stud, collapse of the stud is possible. Collapse of the stud (220) in turn may cause an electrical disconnection to occur at that position, thereby bringing about adverse effects such as improper operation of a finished product having this structure as part thereof. In such an embodiment as shown in FIG. 10, it is difficult to secure the layer material 230 to stud (220) to form a strong bond between the two (along interface A) . Reduced joining strength may result, e.g., due to a slight amount of impurities (such as dust) mixed into the interface, thereby causing the interface to be separated and a gap to appear. Corrosion may then occur, which can then of course adversely affect the resulting product's reliability.
It is believed, therefore, that a printed wiring board made in accordance with procedures which obviate those adverse features cited hereinabove, would constitute a significant advancement in the art. It is further believed that such a procedure would also represent an art advancement.